1. Field of the Invention
The synchronous optical network (SONET) is a new ANSI standard for advanced fiber optic transmission. SONET defines a standard optical interface that allows mid-span meets between equipment produced by different manufacturers. Therefore, the rate conversion of SONET clock rate-derived data to a clock rate suitable for data communication integrated circuits is and for some time to come will be a common operation in telecommunication systems. To accomplish this, it is necessary to rate convert serial streams containing multiple 8-bit time slots from one clock rate to another in dual directions with a minimal amount of circuitry. A principal focus of such an approach would be to provide an implementation that is tolerate of long- or short-term variation in the clock signals. An example is the ability to convert numerous data communication channels that are embedded in a SONET overhead data link (ODL) from a higher data flowrate of 6.48 Mb/s to a lower data communications channel (DCC) integrated circuit data flowrate of 4.096 Mb/s with tolerance for jitter that may arise from the conversion process.
2. Description of Related Art
Many serial rate conversion circuits use dual port RAMs or FIFOs. These circuits convert the data from serial to parallel and back to serial in the rate conversion process. The payload traffic in these solutions is usually not tolerate of jitter or wander in the clock signals. Consequently, traffic often will be lost if any short- or long-term variation arises from the rate conversion.
Conventional approaches that convert the serial data to parallel store the data as 8-bit parallel data in a first set of RAMs and RAM buffers. Then, the 8-bit parallel data is read into a different set of RAMs and RAM buffers to be read out serially. The 8-bit parallel data is converted to a serial format having the desired rate. A significant problem with the conventional way of converting from one serial data flowrate to another is the significant amount of circuitry necessary to convert the serial data to parallel data and the resulting parallel data into serial data. This requires external RAM and the use of at least two field programmable gate arrays.